Write through policy is enabled for cache to memory update, can cache inconsistency or cache incoherency happen?

Learning Goal: I’m working on a operating systems writing question and need an explanation and answer to help me learn.1. Describe similarities of handling a hardware interrupt and handling a software run time exception. 2. A multicore processor has separate on-chip L1 and L2 caches per core, assuming write through policy is enabled for cache to memory update, can cache inconsistency or cache incoherency happen? why? 3. Suppose the following code is carried out by a user program in a virtual machine running on top of a type I hypervisor. Describe the details of the process how the VM user program, VM kernel, the hypervisor, and hardware work together to execute the code and handle run-time conditions. printf(“hello world”); int *ptr = null; *ptr = 5; 4. A system has two CPU cores and two types of pending I/O requests. Processes P22 and P17 are executing. P7 and P3 (first in the queue) are waiting for a socket write to complete. P4 (first in the queue) and P31 are waiting on persistent storage access. P52 (first in the queue) and P29 are awaiting to be scheduled on the CPU. Draw a process queueing diagram for these processes (note each type of I/O has its own waiting queue). Draw arrows of where exactly the processes would go (change of queues) if P4 completes the wait, and P22 tries to open a file. Write the state that each process is in next to the process bubble. 5. Suppose you are developing a multi-threaded Web 3.0 app for digital art creation, management, and merchandising. Thread A is for authoring the digital arts, thread B is for periodically uploading and saving digital arts to a blockchain storage, thread C is for negotiating with requests from digital art marketplaces for purchasing the digital arts. Threads D, E, F are CPU bound threads, they work with each other to execute a machine learning algorithm analyzing viewing stats to find direct advertising opportunities to further monetize the digital arts. Consider using the hybrid threading model, which multiplexing mapping (1 to 1, or many to 1) between each user level thread (A, B, C, D, E, F) and kernel level threads would you use given the following CPU resources, and why? (Hint: Threads A, B, and C are I/O bound threads.) 1) A single core uniprocessor machine 2) A multiple CPU core machine
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